1. Field of the Invention
This invention relates to fault detection circuits, and, more particularly, it relates to a circuit with two modules where each module checks the output of the other module.
2. Description of the Prior Art
Computers and other electronic systems comprise many interconnected modules. Such modules may be large scale functional units such as central processing unit, or they may be integrated circuit chips. The failure of any module can have catastrophic consequences, particularly if such failure is not immediately detected.
It is known in the art to employ duplicate modules and run them in close synchrony for the purpose of detecting faults. For example, duplicate modules are connected in such a manner as to receive identical inputs, and the outputs are compared by a third module which generates an error signal if the outputs disagree. The efficacy of such techniques is limited because they require a separate, off-chip part which is itself subject to latent failure. Undetected failures in the comparison circuit may prevent the discovery of faults in the module being checked.
Techniques have been developed to integrate the error detection circuitry into the duplicated module. For example, U.S. Pat. No. 4,176,258 discloses an integrated circuit chip with a logic circuit and a comparator. Two of these chips can be connected in parallel with one chip having its output enabled and the other chip having its output disabled. The disabled chip becomes a checker, or slave, comparing the output of the enabled master chip to its own internal logic results. This approach obviates the need for a third module while allowing for the use of two identical chips with a single part number. However, it does not provide a way to detect faults in the checker during normal operation. If the checker fails, either in its entirety or in its comparison circuit, faults in the master chip can go undetected.